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ffmpeg-mmx.h
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1 /*
2  * mmx.h
3  * Copyright (C) 1997-2001 H. Dietz and R. Fisher
4  *
5  * This file is part of FFmpeg.
6  *
7  * FFmpeg is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * FFmpeg is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with FFmpeg; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20  */
21 #ifndef AVCODEC_X86_MMX_H
22 #define AVCODEC_X86_MMX_H
23 
24 #include <mythconfig.h>
25 
26 #if HAVE_MMX
27 
28 /*
29  * The type of an value that fits in an MMX register (note that long
30  * long constant values MUST be suffixed by LL and unsigned long long
31  * values by ULL, lest they be truncated by the compiler)
32  */
33 
34 /* Note: moved uq to be first so we can initialize with ULL
35  * in C++11 code without narrowing complaints or use of gcc
36  * extensions. -- Daniel Kristjansson 2012-12-13
37  */
38 
39 typedef union {
40  unsigned long long uq; /* Unsigned Quadword */
41  long long q; /* Quadword (64-bit) value */
42  int d[2]; /* 2 Doubleword (32-bit) values */
43  unsigned int ud[2]; /* 2 Unsigned Doubleword */
44  short w[4]; /* 4 Word (16-bit) values */
45  unsigned short uw[4]; /* 4 Unsigned Word */
46  char b[8]; /* 8 Byte (8-bit) values */
47  unsigned char ub[8]; /* 8 Unsigned Byte */
48  float s[2]; /* Single-precision (32-bit) value */
49 } mmx_t; /* On an 8-byte (64-bit) boundary */
50 
51 
52 #define mmx_i2r(op,imm,reg) \
53  __asm__ volatile (#op " %0, %%" #reg \
54  : /* nothing */ \
55  : "i" (imm) )
56 
57 #define mmx_a2r(op,a_off,a_reg,reg) \
58  __asm__ __volatile__ (#op " " #a_off "(%0), %%" #reg \
59  : /* nothing */ \
60  : "r" (a_reg))
61 
62 #define mmx_m2r(op,mem,reg) \
63  __asm__ volatile (#op " %0, %%" #reg \
64  : /* nothing */ \
65  : "m" (mem))
66 
67 #define mmx_a2r(op,a_off,a_reg,reg) \
68  __asm__ __volatile__ (#op " " #a_off "(%0), %%" #reg \
69  : /* nothing */ \
70  : "r" (a_reg))
71 
72 #define mmx_r2m(op,reg,mem) \
73  __asm__ volatile (#op " %%" #reg ", %0" \
74  : "=m" (mem) \
75  : /* nothing */ )
76 
77 #define mmx_r2a(op,reg,a_off,a_reg) \
78  __asm__ __volatile__ (#op " %%" #reg ", " #a_off "(%0)" \
79  : /* nothing */ \
80  : "r"(a_reg))
81 
82 #define mmx_r2r(op,regs,regd) \
83  __asm__ volatile (#op " %" #regs ", %" #regd)
84 
85 
86 #define emms() __asm__ volatile ("emms")
87 
88 #define movd_m2r(var,reg) mmx_m2r (movd, var, reg)
89 #define movd_r2m(reg,var) mmx_r2m (movd, reg, var)
90 #define movd_r2r(regs,regd) mmx_r2r (movd, regs, regd)
91 #define movd_v2r(var,reg) __asm__ __volatile__ ("movd %0, %%" #reg \
92  : /* nothing */ \
93  : "rm" (var))
94 #define movd_r2v(reg,var) __asm__ __volatile__ ("movd %%" #reg ", %0" \
95  : "=rm" (var) \
96  : /* nothing */ )
97 
98 #define movq_m2r(var,reg) mmx_m2r (movq, var, reg)
99 #define movq_a2r(off,var,reg) mmx_a2r (movq, off, var, reg)
100 #define movq_r2m(reg,var) mmx_r2m (movq, reg, var)
101 #define movq_r2r(regs,regd) mmx_r2r (movq, regs, regd)
102 #define movq_r2a(reg,off,var) mmx_r2a (movq, reg, off, var)
103 
104 #define packssdw_m2r(var,reg) mmx_m2r (packssdw, var, reg)
105 #define packssdw_r2r(regs,regd) mmx_r2r (packssdw, regs, regd)
106 #define packsswb_m2r(var,reg) mmx_m2r (packsswb, var, reg)
107 #define packsswb_r2r(regs,regd) mmx_r2r (packsswb, regs, regd)
108 
109 #define packuswb_m2r(var,reg) mmx_m2r (packuswb, var, reg)
110 #define packuswb_r2r(regs,regd) mmx_r2r (packuswb, regs, regd)
111 
112 #define paddb_m2r(var,reg) mmx_m2r (paddb, var, reg)
113 #define paddb_r2r(regs,regd) mmx_r2r (paddb, regs, regd)
114 #define paddd_m2r(var,reg) mmx_m2r (paddd, var, reg)
115 #define paddd_r2r(regs,regd) mmx_r2r (paddd, regs, regd)
116 #define paddw_m2r(var,reg) mmx_m2r (paddw, var, reg)
117 #define paddw_r2r(regs,regd) mmx_r2r (paddw, regs, regd)
118 
119 #define paddsb_m2r(var,reg) mmx_m2r (paddsb, var, reg)
120 #define paddsb_r2r(regs,regd) mmx_r2r (paddsb, regs, regd)
121 #define paddsw_m2r(var,reg) mmx_m2r (paddsw, var, reg)
122 #define paddsw_r2r(regs,regd) mmx_r2r (paddsw, regs, regd)
123 
124 #define paddusb_m2r(var,reg) mmx_m2r (paddusb, var, reg)
125 #define paddusb_r2r(regs,regd) mmx_r2r (paddusb, regs, regd)
126 #define paddusw_m2r(var,reg) mmx_m2r (paddusw, var, reg)
127 #define paddusw_r2r(regs,regd) mmx_r2r (paddusw, regs, regd)
128 
129 #define pand_m2r(var,reg) mmx_m2r (pand, var, reg)
130 #define pand_r2r(regs,regd) mmx_r2r (pand, regs, regd)
131 
132 #define pandn_m2r(var,reg) mmx_m2r (pandn, var, reg)
133 #define pandn_r2r(regs,regd) mmx_r2r (pandn, regs, regd)
134 
135 #define pcmpeqb_m2r(var,reg) mmx_m2r (pcmpeqb, var, reg)
136 #define pcmpeqb_r2r(regs,regd) mmx_r2r (pcmpeqb, regs, regd)
137 #define pcmpeqd_m2r(var,reg) mmx_m2r (pcmpeqd, var, reg)
138 #define pcmpeqd_r2r(regs,regd) mmx_r2r (pcmpeqd, regs, regd)
139 #define pcmpeqw_m2r(var,reg) mmx_m2r (pcmpeqw, var, reg)
140 #define pcmpeqw_r2r(regs,regd) mmx_r2r (pcmpeqw, regs, regd)
141 
142 #define pcmpgtb_m2r(var,reg) mmx_m2r (pcmpgtb, var, reg)
143 #define pcmpgtb_r2r(regs,regd) mmx_r2r (pcmpgtb, regs, regd)
144 #define pcmpgtd_m2r(var,reg) mmx_m2r (pcmpgtd, var, reg)
145 #define pcmpgtd_r2r(regs,regd) mmx_r2r (pcmpgtd, regs, regd)
146 #define pcmpgtw_m2r(var,reg) mmx_m2r (pcmpgtw, var, reg)
147 #define pcmpgtw_r2r(regs,regd) mmx_r2r (pcmpgtw, regs, regd)
148 
149 #define pmaddwd_m2r(var,reg) mmx_m2r (pmaddwd, var, reg)
150 #define pmaddwd_a2r(of,var,reg) mmx_a2r (pmaddwd, of, var, reg)
151 #define pmaddwd_r2r(regs,regd) mmx_r2r (pmaddwd, regs, regd)
152 
153 #define pmulhw_m2r(var,reg) mmx_m2r (pmulhw, var, reg)
154 #define pmulhw_r2r(regs,regd) mmx_r2r (pmulhw, regs, regd)
155 
156 #define pmullw_m2r(var,reg) mmx_m2r (pmullw, var, reg)
157 #define pmullw_r2r(regs,regd) mmx_r2r (pmullw, regs, regd)
158 
159 #define por_m2r(var,reg) mmx_m2r (por, var, reg)
160 #define por_r2r(regs,regd) mmx_r2r (por, regs, regd)
161 
162 #define pslld_i2r(imm,reg) mmx_i2r (pslld, imm, reg)
163 #define pslld_m2r(var,reg) mmx_m2r (pslld, var, reg)
164 #define pslld_r2r(regs,regd) mmx_r2r (pslld, regs, regd)
165 #define psllq_i2r(imm,reg) mmx_i2r (psllq, imm, reg)
166 #define psllq_m2r(var,reg) mmx_m2r (psllq, var, reg)
167 #define psllq_r2r(regs,regd) mmx_r2r (psllq, regs, regd)
168 #define psllw_i2r(imm,reg) mmx_i2r (psllw, imm, reg)
169 #define psllw_m2r(var,reg) mmx_m2r (psllw, var, reg)
170 #define psllw_r2r(regs,regd) mmx_r2r (psllw, regs, regd)
171 
172 #define psrad_i2r(imm,reg) mmx_i2r (psrad, imm, reg)
173 #define psrad_m2r(var,reg) mmx_m2r (psrad, var, reg)
174 #define psrad_r2r(regs,regd) mmx_r2r (psrad, regs, regd)
175 #define psraw_i2r(imm,reg) mmx_i2r (psraw, imm, reg)
176 #define psraw_m2r(var,reg) mmx_m2r (psraw, var, reg)
177 #define psraw_r2r(regs,regd) mmx_r2r (psraw, regs, regd)
178 
179 #define psrld_i2r(imm,reg) mmx_i2r (psrld, imm, reg)
180 #define psrld_m2r(var,reg) mmx_m2r (psrld, var, reg)
181 #define psrld_r2r(regs,regd) mmx_r2r (psrld, regs, regd)
182 #define psrlq_i2r(imm,reg) mmx_i2r (psrlq, imm, reg)
183 #define psrlq_m2r(var,reg) mmx_m2r (psrlq, var, reg)
184 #define psrlq_r2r(regs,regd) mmx_r2r (psrlq, regs, regd)
185 #define psrlw_i2r(imm,reg) mmx_i2r (psrlw, imm, reg)
186 #define psrlw_m2r(var,reg) mmx_m2r (psrlw, var, reg)
187 #define psrlw_r2r(regs,regd) mmx_r2r (psrlw, regs, regd)
188 
189 #define psubb_m2r(var,reg) mmx_m2r (psubb, var, reg)
190 #define psubb_r2r(regs,regd) mmx_r2r (psubb, regs, regd)
191 #define psubd_m2r(var,reg) mmx_m2r (psubd, var, reg)
192 #define psubd_r2r(regs,regd) mmx_r2r (psubd, regs, regd)
193 #define psubw_m2r(var,reg) mmx_m2r (psubw, var, reg)
194 #define psubw_r2r(regs,regd) mmx_r2r (psubw, regs, regd)
195 
196 #define psubsb_m2r(var,reg) mmx_m2r (psubsb, var, reg)
197 #define psubsb_r2r(regs,regd) mmx_r2r (psubsb, regs, regd)
198 #define psubsw_m2r(var,reg) mmx_m2r (psubsw, var, reg)
199 #define psubsw_r2r(regs,regd) mmx_r2r (psubsw, regs, regd)
200 
201 #define psubusb_m2r(var,reg) mmx_m2r (psubusb, var, reg)
202 #define psubusb_r2r(regs,regd) mmx_r2r (psubusb, regs, regd)
203 #define psubusw_m2r(var,reg) mmx_m2r (psubusw, var, reg)
204 #define psubusw_r2r(regs,regd) mmx_r2r (psubusw, regs, regd)
205 
206 #define punpckhbw_m2r(var,reg) mmx_m2r (punpckhbw, var, reg)
207 #define punpckhbw_r2r(regs,regd) mmx_r2r (punpckhbw, regs, regd)
208 #define punpckhdq_m2r(var,reg) mmx_m2r (punpckhdq, var, reg)
209 #define punpckhdq_r2r(regs,regd) mmx_r2r (punpckhdq, regs, regd)
210 #define punpckhwd_m2r(var,reg) mmx_m2r (punpckhwd, var, reg)
211 #define punpckhwd_r2r(regs,regd) mmx_r2r (punpckhwd, regs, regd)
212 
213 #define punpcklbw_m2r(var,reg) mmx_m2r (punpcklbw, var, reg)
214 #define punpcklbw_r2r(regs,regd) mmx_r2r (punpcklbw, regs, regd)
215 #define punpckldq_m2r(var,reg) mmx_m2r (punpckldq, var, reg)
216 #define punpckldq_r2r(regs,regd) mmx_r2r (punpckldq, regs, regd)
217 #define punpcklwd_m2r(var,reg) mmx_m2r (punpcklwd, var, reg)
218 #define punpcklwd_r2r(regs,regd) mmx_r2r (punpcklwd, regs, regd)
219 
220 #define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg)
221 #define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd)
222 
223 
224 /* 3DNOW extensions */
225 
226 #define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg)
227 #define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd)
228 
229 
230 /* AMD MMX extensions - also available in intel SSE */
231 
232 
233 #define mmx_m2ri(op,mem,reg,imm) \
234  __asm__ volatile (#op " %1, %0, %%" #reg \
235  : /* nothing */ \
236  : "m" (mem), "i" (imm))
237 #define mmx_r2ri(op,regs,regd,imm) \
238  __asm__ volatile (#op " %0, %%" #regs ", %%" #regd \
239  : /* nothing */ \
240  : "i" (imm) )
241 
242 #define mmx_fetch(mem,hint) \
243  __asm__ volatile ("prefetch" #hint " %0" \
244  : /* nothing */ \
245  : "m" (mem))
246 
247 
248 #define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg)
249 
250 #define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var)
251 
252 #define pavgb_m2r(var,reg) mmx_m2r (pavgb, var, reg)
253 #define pavgb_r2r(regs,regd) mmx_r2r (pavgb, regs, regd)
254 #define pavgw_m2r(var,reg) mmx_m2r (pavgw, var, reg)
255 #define pavgw_r2r(regs,regd) mmx_r2r (pavgw, regs, regd)
256 
257 #define pextrw_r2r(mmreg,reg,imm) mmx_r2ri (pextrw, mmreg, reg, imm)
258 
259 #define pinsrw_r2r(reg,mmreg,imm) mmx_r2ri (pinsrw, reg, mmreg, imm)
260 
261 #define pmaxsw_m2r(var,reg) mmx_m2r (pmaxsw, var, reg)
262 #define pmaxsw_r2r(regs,regd) mmx_r2r (pmaxsw, regs, regd)
263 
264 #define pmaxub_m2r(var,reg) mmx_m2r (pmaxub, var, reg)
265 #define pmaxub_r2r(regs,regd) mmx_r2r (pmaxub, regs, regd)
266 
267 #define pminsw_m2r(var,reg) mmx_m2r (pminsw, var, reg)
268 #define pminsw_r2r(regs,regd) mmx_r2r (pminsw, regs, regd)
269 
270 #define pminub_m2r(var,reg) mmx_m2r (pminub, var, reg)
271 #define pminub_r2r(regs,regd) mmx_r2r (pminub, regs, regd)
272 
273 #define pmovmskb(mmreg,reg) \
274  __asm__ volatile ("movmskps %" #mmreg ", %" #reg)
275 
276 #define pmulhuw_m2r(var,reg) mmx_m2r (pmulhuw, var, reg)
277 #define pmulhuw_r2r(regs,regd) mmx_r2r (pmulhuw, regs, regd)
278 
279 #define prefetcht0(mem) mmx_fetch (mem, t0)
280 #define prefetcht1(mem) mmx_fetch (mem, t1)
281 #define prefetcht2(mem) mmx_fetch (mem, t2)
282 #define prefetchnta(mem) mmx_fetch (mem, nta)
283 
284 #define psadbw_m2r(var,reg) mmx_m2r (psadbw, var, reg)
285 #define psadbw_r2r(regs,regd) mmx_r2r (psadbw, regs, regd)
286 
287 #define pshufw_m2r(var,reg,imm) mmx_m2ri(pshufw, var, reg, imm)
288 #define pshufw_r2r(regs,regd,imm) mmx_r2ri(pshufw, regs, regd, imm)
289 
290 #define sfence() __asm__ volatile ("sfence\n\t")
291 
292 /* SSE2 */
293 #define pshufhw_m2r(var,reg,imm) mmx_m2ri(pshufhw, var, reg, imm)
294 #define pshufhw_r2r(regs,regd,imm) mmx_r2ri(pshufhw, regs, regd, imm)
295 #define pshuflw_m2r(var,reg,imm) mmx_m2ri(pshuflw, var, reg, imm)
296 #define pshuflw_r2r(regs,regd,imm) mmx_r2ri(pshuflw, regs, regd, imm)
297 
298 #define pshufd_r2r(regs,regd,imm) mmx_r2ri(pshufd, regs, regd, imm)
299 
300 #define movdqa_m2r(var,reg) mmx_m2r (movdqa, var, reg)
301 #define movdqa_r2m(reg,var) mmx_r2m (movdqa, reg, var)
302 #define movdqa_r2r(regs,regd) mmx_r2r (movdqa, regs, regd)
303 #define movdqu_m2r(var,reg) mmx_m2r (movdqu, var, reg)
304 #define movdqu_r2m(reg,var) mmx_r2m (movdqu, reg, var)
305 #define movdqu_r2r(regs,regd) mmx_r2r (movdqu, regs, regd)
306 
307 #define pmullw_r2m(reg,var) mmx_r2m (pmullw, reg, var)
308 
309 #define pslldq_i2r(imm,reg) mmx_i2r (pslldq, imm, reg)
310 #define psrldq_i2r(imm,reg) mmx_i2r (psrldq, imm, reg)
311 
312 #define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd)
313 #define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd)
314 
315 #endif
316 
317 #endif /* AVCODEC_X86_MMX_H */
static const uint16_t * d